Fast decoding algorithm for first order DC-input sigma-delta modulators

In this paper, a new decoding technique is described for first order low frequency sigma-delta modulators. This technique, with less number of operations than available decoders, is proposed for low speed sensing devices in lab-on-chip applications. The decoding process is based on an iterative dynamic decoding algorithm. The simulation results present significant improvement in term of number of operations when applied to a first-order sigma-delta modulator. The gain in the term of number of iterations is 4.013 dB for an 8-bit sequence and 1.697 dB for an 80-bit sequence.