5.4 GOPS linear array architecture DSP for video-format conversion

Author

Kurokawa, M. ; Hashiguchi, A. ; Nakamura, K. ; Okuda, H. ; Aoyama, K. ; Yamazaki, T. ; Ohki, M. ; Soneda, M. ; Seno, K. ; Kumata, I. ; Aikawa, M. ; Hanaki, H. ; Iwase, S.

Author_Institution

Sony Corp., Tokyo, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

254

Lastpage

255

Abstract

A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.

Keywords

digital signal processing chips; high definition television; parallel architectures; television equipment; video signal processing; 75 MHz; HDTV signals; SIMD processor elements; Y/C separation; image enhancement; image-size conversion; linear array architecture; noise reduction; picture quality; programmable DSP; real-time video processing; video format conversion; Arithmetic; Blanking; Circuits; Clocks; Decoding; Digital signal processing; HDTV; Image converters; Pipelines; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488594

Filename

488594