A 212 Mb/s Chip for 4 × 4 16-QAM V-BLAST decoder

This paper presents the design of a 212 Mb/s chip for Vertical Bell Labs Layered Space-Time (V-BLAST) detection for a 4 x 4 16-QAM MIMO wireless communication system based on the QR factorization technique. We employ Coordinate Rotation Digital Computer (CORDIC) rotator processors for pre decoder block. We implement back substitution Symbol Interference Cancellation (SIC) block without the use of division and multiplication hardware, reducing the hardware cost, without compromising the numerical stability. The proposed VLSI architecture on a 0.18 mum Application Specific Integrated Circuits (ASIC) platform achieves a throughput of 212 Mb/s with an equivalent gate count of 70 k with a core of 1 mm² at 140 MHz clock frequency.