High-speed low-complexity Golay decoder based on syndrome-weight determination

In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the parallel hardware design by using two syndromes. For some common FPGA technology the complete system occupies only 666 logic elements and the time delay is 25.9 ns; for a 0.18-¿m CMOS technology the result is a 0.026 mm² area and a 2.58 Gbps throughput.