A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

This paper proposes a new current-mode incremental signaling parallel link interface with per-pin skew compensation. Per-pin skew compensation is carried out in a training phase where clock-like training data are sent to all channels along with a reference clock of the same frequency. Training data are deskewed with respect to the common reference clock using DLLs such that all channels are skew-compensated simultaneously. New encoding and decoding scheme have been proposed to reduce the signal critical path at the transmitter. Transimpedance amplifiers with replica biasing are used to perform current-to-voltage conversion at the receiving end with a minimum sensitivity to supply voltage fluctuation. To evaluate the performance of the proposed skew compensating technique, a parallel link interface consisting of two data channels and one reference clock channel has been implemented with UMC 0.13 mum 1.2 V CMOS technology and analyzed using SpectreRF from cadence design systems with BIM3V3 device models. The channels are modeled as 50 Omega microstrip lines. Simulation results have demonstrated that the proposed parallel link interface is capable of deskewing the channel signals at 1 Gbytes/s.