Design of a quadrature decoder/counter interface IC for motor control using CPLD

In this paper we present the design of a quadrature decoder/counter interface IC (ASIC) that performs the decoding, counting, and bus interface function in digital motor control systems, employing an Altera FLEX 10 KA CPLD device. The ASIC contains a pair of digital filters, a quadrature decoder, an up/down counter, a latch and inhibit circuit, and an 8-bit bus interface to a digital processing system. The design of the digital filter is based on the finite state machine model with datapath (FSMD). A novel scheme for detecting the motor rotation direction is also proposed. The ASIC can be applied to a digital motor control system for getting the rotation speed or position of the motor, which is equipped with an optical encoder. The data acquisition can be extended to 16-bit integer format by two continuous reading cycles. Simulation and experimental tests are shown to verify the ASIC functions properly.