DocumentCode :
3270695
Title :
Partially-parallel irregular LDPC decoder based on improved message passing schedule
Author :
LI, Xing ; Shimizu, Kazunori ; Qiu, Zhen ; Ikenaga, Takeshi ; Goto, Satoshi
Author_Institution :
Waseda Univ., Fukuoka
fYear :
2007
fDate :
5-8 Aug. 2007
Firstpage :
1473
Lastpage :
1476
Abstract :
In this paper, we propose a new efficient message-passing schedule for irregular LPDC code. Our approach is based on the schedule designed for regular LDPC code. We have modified the original schedule for regular LDPC code and improved it particularly for the irregular LDPC coder realization. The experimental results show that our method could achieve better performance than conventional one, and improve the converging rate as well.
Keywords :
decoding; message passing; parity check codes; scheduling; message passing schedule; partially-parallel irregular LDPC decoder; regular LDPC code; Bit error rate; CMOS technology; Decoding; Error correction codes; Hardware; Message passing; Parity check codes; Processor scheduling; Production systems; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
ISSN :
1548-3746
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2007.4488821
Filename :
4488821
Link To Document :
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