An effective fault-tolerant technique for circular butterfly parallel systems

Author

Nian-Feng Tzeng

Author_Institution

Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA

fYear

1990

fDate

9-13 Dec 1990

Firstpage

223

Lastpage

226

Abstract

The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI/WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures. A resulting butterfly system with L levels involves (1/log₂L)% spare PEs and roughly 50% additional links. Reconfiguration in response fault is easy and can be performed in a distributed manner. The analytic results show that the proposed design exhibits significantly improved reliability

Keywords

fault tolerant computing; multiprocessor interconnection networks; parallel machines; circular butterfly parallel systems; fault-tolerant technique; interconnection pattern; reconfiguration; reliability; rigid full butterfly structure; Concurrent computing; Environmental economics; Fault tolerant systems; Parallel architectures; Process design; Reliability; Topology; Very large scale integration; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on

Conference_Location

Dallas, TX

Print_ISBN

0-8186-2087-0

Type

conf

DOI

10.1109/SPDP.1990.143537

Filename

143537