Parallel algorithms for slicing floorplan designs

Floorplan design is the first task in VLSI layout and perhaps the most important one. It is the problem of allocating space to a set of modules in the plane in order to minimize the area of the bounding rectangle. The authors present a parallel algorithm for finding a minimum area slicing floorplan that respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors. It is based on a new O(n²) sequential algorithm for solving the above problem