Design of a highly parallel IEEE standard floating point unit: the Cyrix 83D87 coprocessor

Summary form only given. The author describes a highly parallel integrated floating point multiply/divide/square root unit which can achieve optimal speedup with regards to the typical O(n²) implementation cost of these operations. The core is a redundant binary adder tree realizing a rectangular aspect ratio multiplier. The author shows that an optimal aspect ratio for such a rectangular aspect ratio multiplier is log n to 1, in that O(n²/log n) bit level processors can then be employed in parallel to realize the product of two n bit numbers in O(log n) time. He describes new divide and square root algorithms employing the concept of a `short reciprocal´ to exploit the features of such a rectangular aspect ratio multiplier. The incorporation of these algorithms in the design of an IEEE standard floating point unit is discussed. The realization of these techniques in the implementation of the IEEE standard Cyrix 83D87 coprocessor is described