A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve Cryptosystems

Hyper elliptic curve cryptosystem (HECC) is much more efficient than RSA and elliptic curve cryptosystem (ECC) for its shorter key lengths. Hyper elliptic curve cryptosystems can be sped up by parallel execution on hardware accelerators, yet none of previous efforts can sufficiently support parallel processing with reasonable resources. In this paper, we propose a new parallel processor architecture for HECC, which supports sufficient instruction-level parallel processing. In the architecture, Parallel finite field (FF) cores are designed, and each core consists of a control unit, a register file, an ALU and a ROM. Instruction-level parallelism (ILP) with pipeline is achieved in this architecture. The results show that the implementation can achieve much better performance than other hardware implementations done to date.