• DocumentCode
    3271231
  • Title

    Lowering the latency of interfaces for rationally-related frequencies

  • Author

    Chabloz, Jean-Michel ; Hemani, Ahmed

  • Author_Institution
    Dept. of Electron. Syst., KTH - R. Inst. of Technol., Stockholm, Sweden
  • fYear
    2010
  • fDate
    3-6 Oct. 2010
  • Firstpage
    23
  • Lastpage
    30
  • Abstract
    We have introduced the Globally-Ratiochronous, Locally-Synchronous (GRLS) design paradigm, a design style based on rationally-related frequencies, with the objective to overcome the limitations of traditional multi-frequency systems by providing a flexibility close that of Globally-Asynchronous, Locally-Synchronous (GALS) systems but introducing performance penalties and overheads close to those of mesochronous systems. In this paper we focus on performances and improve the latency figures of our original GRLS interfaces by introducing two new interfaces, called GRLS-F and GRLS-noF, the first suitable for blocks with long computation time and the second for blocks with short computation time. The latency figures of the original GRLS interfaces are improved up to 50% without increasing complexity. The average latency figures of the resulting interfaces are lower than 1 Receiver clock cycle, the latency of a synchronous interface.
  • Keywords
    clocks; peripheral interfaces; clock cycle; clock generation unit; flexibility; globally-ratiochronous, locally-synchronous design; interface latency; mesochronous system; multifrequency system; performance overhead; performance penalty; rationally-related frequencies; synchronous interface; Clocks; Complexity theory; Jitter; Receivers; Synchronization; Throughput; Transmitters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2010 IEEE International Conference on
  • Conference_Location
    Amsterdam
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-8936-7
  • Type

    conf

  • DOI
    10.1109/ICCD.2010.5647563
  • Filename
    5647563