Design of Prefix-Based Optimal Reversible Comparator

This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bit comparator where two outputs, g_i indicating A_i >; B_i and e_i indicating A_i = B_i, are generated for i^th operand bits. The outputs of 1-bit comparator stage are grouped in the second stage using prefix grouping and the final outputs G indicating A >; B and E indicating A=B are generated. In the last stage the outputs of second stage i.e. G and E are used to generate L signal indicating A <; B. The proposed 64-bit comparator design results in 63% reduced quantum delay, 21% reduced quantum cost and 16% reduced garbage outputs when compared with the best existing design of tree based comparator.