A 12 b 10 MHz 250 mW CMOS A/D converter

In high-speed and high-resolution ADCs, self-calibration techniques have widely been used to improve linearities by subtracting ADC nonlinear errors in digital domain. However, stand-alone self-calibrated ADC systems employing a CMOS process have not been fully integrated on a single chip. This fully-differential 12 b 4-stage pipelined CMOS ADC uses a modified digital-domain nonlinear error calibration technique. All functional blocks including digital calibration logic, 16 B memory, and bias circuits are fully integrated on a single chip. The ADC is optimized to improve linearity and yield and uses a mid-rise coding technique that is more efficient in using identical circuit blocks repeatedly than a conventional mid-tread coding. As a result, a modular circuit design approach is applied to the proposed ADC, easily modified for 10 b or 14 b resolution by eliminating or adding an identical stage.