DocumentCode
3271344
Title
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders
Author
Vudadha, Chetan ; Phaneendra, P. Sai ; Ahmed, Syed Ershad ; Sreehari, V. ; Muthukrishnan, N.M. ; Srinivas, M.B.
Author_Institution
Dept. of Electr. & Electron. Eng., Birla Inst. of Technol. & Sci.-Pilani, Hyderabad, India
fYear
2012
fDate
19-21 Aug. 2012
Firstpage
225
Lastpage
230
Abstract
Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design and analysis of reversible ripple, prefix and prefix ripple hybrid adders. Firstly an analysis and comparison of all the existing reversible ripple carry adders is presented. The reversible ripple carry adders are characterized by high quantum depth, low quantum cost and/or low garbage outputs and ancilla inputs bits. Secondly design methodology for reversible prefix adders is presented. The reversible prefix adders are characterized by low quantum depth, high quantum cost and/or high garbage outputs and ancilla inputs bits. Finally design of the proposed reversible prefix-ripple hybrid adders is presented and comparison of the different parameters of reversible ripple, prefix and prefix-ripple hybrid adders is illustrated.
Keywords
adders; logic design; nanoelectronics; optical computing; quantum computing; nanotechnology; optical computing; prefix adder design; prefix-ripple hybrid adder design; quantum computing; reversible computing; reversible prefix-ripple hybrid adder; reversible ripple adder design; Adders; Computer architecture; Indexes; Logic gates; Microprocessors; Quantum computing; Silicon; Emerging Technologies; Hybrid; Prefix adders; Quantum Computing; Reversible Logic; Ripple adders;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
Conference_Location
Amherst, MA
ISSN
2159-3469
Print_ISBN
978-1-4673-2234-8
Type
conf
DOI
10.1109/ISVLSI.2012.50
Filename
6296477
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