Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit

In this paper a heterogeneous Multiprocessor System on-Chip (MPSoC) is controlled by a dynamic task scheduling unit called Core Manager. The instruction set architecture of this unit is extended to improve performance for dynamic data dependency checking, task scheduling, processing element (PE) allocation and data transfer management. In order to analyze and compare different implementations and trade-offs a tool flow was developed. Area and timing results are provided as well. A significant performance improvement can be shown for all parts of the Core Manager.