A parallel simulation approach to optimum circuit design

A circuit partitioning and parallel processing approach is applied to optimum circuit designs to achieve a significant speed-up in computation time. Numerical examples are given to illustrate the approach and to estimate the speed-up factors which are contributed by the partitioning algorithm employed, the choice of subcircuit partitioning with regard to circuit design parameters, and the number of processors used. The application of circuit partitioning and parallel processing to optimum circuit design via the SPICE program is shown to yield three potential speed-up factors which can reduce the SPICE computation times. There is a speed-up factor due to the choice of subcircuit partitioning and the selection of which subcircuits are effected by design parameter optimization. Another factor is attributable to the partitioning of subcircuits which decomposes one large circuit equation into multiple, smaller subcircuit equations; the solution time for these subcircuit equations is much smaller than the time required to solve one large circuit equation. Finally, since the computations for each subcircuit and/or for each frequency (for AC analysis) are independent, they may be performed concurrently on multiple processors, giving a further potential speed-up factor