A 64-entry 167 MHz fully-associative TLB for a RISC microprocessor

Author

Anderson, E.

Author_Institution

Sun Microsystems Inc., Mountain View, CA, USA

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

360

Lastpage

361

Abstract

Memory subsystems of RISC microprocessors require efficient translation of virtual addresses to physical addresses. A fully-associative embedded translation lookaside buffer (TLB) provides this function in a microprocessor. Two identical TLBs are used: one for instructions and another for data. The CPU architecture requires that the TLB translate a new address every cycle.

Keywords

CMOS digital integrated circuits; CMOS memory circuits; buffer storage; content-addressable storage; memory architecture; microprocessor chips; reduced instruction set computing; storage allocation; 167 MHz; CAM array; RISC microprocessor; embedded translation lookaside buffer; fully-associative TLB; memory subsystems; n-well CMOS process; virtual addresses; CADCAM; Central Processing Unit; Clocks; Computer aided manufacturing; Driver circuits; Inverters; Microprocessors; Pulse amplifiers; Reduced instruction set computing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488717

Filename

488717

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3271721