Title :
A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme
Author :
Koike, H. ; Otsuki, T. ; Kimura, T. ; Fukuma, M. ; Hayashi, Y. ; Maejima, Y. ; Amanuma, K. ; Tanabe, N. ; Matsuki, T. ; Saito, S. ; Takeuchi, T. ; Kobayashi, S. ; Kunio, T. ; Hase, T. ; Miyasaka, Y. ; Shohata, N. ; Takada, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
With increase in the capacity of nonvolatile memories, the range of their use has been widening. A nonvolatile ferroelectric RAM (NVFRAM) based on a 1-transistor and 1-capacitor (1T/1C) memory cell has potential for fast-access time and small-chip size comparable with a DRAM. However, previously reported NVFRAMs are still slower than ordinary DRAMs, since driving a cell-plate line in NVFRAMs is slow. To avoid this, a non-driven cell plate line write/read scheme (NDP scheme) is presented which leads to NVFRAMs with as fast access time as DRAMs.
Keywords :
ferroelectric storage; random-access storage; 1 Mbit; 1-transistor 1-capacitor memory cell; 60 ns; NVFRAM; RAM; access time; chip size; nondriven cell plate line write/read scheme; nonvolatile ferroelectric memory; Capacitors; Circuits; Ferroelectric materials; National electric code; Nonvolatile memory; Polarization; Random access memory; Read-write memory; Threshold voltage; Virtual colonoscopy;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488720
