Title :
A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection
Author :
Giacalone, G. ; Busch, R. ; Creed, F. ; Davidovich, A. ; Divakaruni, S. ; Drake, C. ; Ematrudo, C. ; Fifield, J. ; Hodges, M. ; Howell, W. ; Jenkins, Phillip ; Kozyrczak, M. ; Miller, Colin ; Obremski, T. ; Reed, C. ; Rohrbaugh, G. ; Vincent, M. ; von Rey
Author_Institution :
IBM Microelectron. Div., Essex Junction, VT, USA
Abstract :
Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.
Keywords :
DRAM chips; cache storage; error correction codes; multichip modules; 1 MB; 100 MHz; DRAM technology; ECC protection; SRAM technology; electrical characteristics; high-speed single chip; integrated in-line level-2 cache memory; interface; multichip-module packaging; processor connection; Cache memory; Driver circuits; Electric variables; Error correction codes; Logic arrays; Protection; Random access memory; Registers; Space technology; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488721
