A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

Author

Nitta, Yoshinori ; Sakashita, N. ; Shimomura, Kazuya ; Okuda, F. ; Shimano, H. ; Yamakawa, Satoshi ; Furukawa, A. ; Kise, Kenji ; Watanabe, Hiromi ; Toyoda, Yoshiaki ; Fukada, T. ; Hasegawa, Mikio ; Tsukude, M. ; Arimoto, Keisuke ; Baba, S. ; Tomita, Yasu

Author_Institution

Adv. Technol. R&D., Mitsubishi Electr. Corp., Itami, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

376

Lastpage

377

Abstract

This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.

Keywords

DRAM chips; built-in self test; memory architecture; shared memory systems; 1 GB/s; 1 Gbit; 200 MHz; 3D graphics frame memory; built-in self-test circuit; data transfer rate; distributed bank architecture; hierarchical square-shaped memory block; margin test; memory capacity; single DRAM array; synchronous DRAM; time sharing; unified memory system; Built-in self-test; Chip scale packaging; Circuit testing; Clocks; Delay; Layout; Phase locked loops; Random access memory; Signal generators; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488724

Filename

488724