Design and FPGA Implementation of a Pseudo-Random Bit Sequence Generator Using Spatiotemporal Chaos

According to the postulation of Shannon\´s theoretical unbreakable cryptography, in practice, a pseudo-random bit sequence (PRBS) often acts as a "one-time padding" key sequence, therefore should be of good statistical properties, complex structure meanwhile simpleness in implementation. To meet these needs, a spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (field programmable gate array) implementation in present paper. Certain interleaving and truncating processes are introduced into the PRBS generator to avoid the degradation due to digitization. Owing to the exceptional properties of spatiotemporal chaos like the sensitivity to initial conditions and parameters, the mixing and ergodicity characters, and the intrinsic feature of operational parallelism, the proposed PRBS generator not only has good performance in terms of statistical properties, but also has high product throughput being realized by FPGA hardware. The PRBS generator has successfully passed several performance assessments including widely used FIPS 140-2 test and extremely rigorous NIST 800-22 test. An effort of integrating the proposed algorithm into a Xilinx Spartan-III XC3S400 FPGA is also reported. Elementary hardware simulation results show that the throughput of the PRBS generator chip reaches high up to 512 Mbps under a running condition of 50 MHz clock frequency