Title :
Low Power Techniques on a High Speed Floating-point Adder Design
Author :
Zhang, Ge ; Huang, Kun ; Shen, Haihua ; Zhang, Feng
Author_Institution :
Chinese Acad. of Sci. Beijing, Beijing
Abstract :
A 64 bit low power, high speed floating-point adder design is presented in this paper. The proposed floating-point adder is based on dual path architecture, and both dynamic and leakage power are reduced by exploiting architecture opportunities to minimize switching activity and maximize the stack effect of the circuits concurrently. Experimental result based on 130 nm CMOS standard cell design shows that average power consumptions of the FP adder can be reduced by 61.4% with proposed low power techniques.
Keywords :
CMOS digital integrated circuits; adders; floating point arithmetic; high-speed integrated circuits; low-power electronics; CMOS standard cell design; dual path architecture; high speed floating-point adder; low power techniques; power consumptions; size 130 nm; switching activity; word length 64 bit; Adders; CMOS logic circuits; Central Processing Unit; Computer architecture; Delay; Energy consumption; Laboratories; Logic design; Microprocessors; Switching circuits;
Conference_Titel :
Integration Technology, 2007. ICIT '07. IEEE International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
1-4244-1092-4
Electronic_ISBN :
1-4244-1092-4
DOI :
10.1109/ICITECHNOLOGY.2007.4290469
