DocumentCode
3272030
Title
An Innovative Power-Efficient Architecture for Input Buffer of Network on Chip
Author
Huang, Kun ; Wang, Jun ; Zhang, Ge
Author_Institution
Chinese Acad. of Sci., Beijing
fYear
2007
fDate
20-24 March 2007
Firstpage
245
Lastpage
248
Abstract
In recent years, the power efficiency of NoC (network on chip) is becoming a new research direction. For tiled CMP (single-chip multi processor), the characteristics of transmission data of NoC in a tiled CMP should be noticed that the probability of which the transmitted bits are zero is much bigger than that of which the bits are one. This paper proposes an innovative power-efficient architecture of input buffer of NoC, which makes use of the mentioned characteristics, can improve the power efficiency of the NoC of tiled CMP significantly.
Keywords
low-power electronics; microprocessor chips; multiprocessor interconnection networks; network-on-chip; innovative power-efficient architecture; network on chip input buffer; network on chip power efficiency; single-chip multi processor; Buffer storage; Computer architecture; Computer networks; Delay; Energy consumption; Laboratories; Microprocessors; Network-on-a-chip; Routing; System-on-a-chip; input buffer; network on chip; power-efficient; tiled CMP;
fLanguage
English
Publisher
ieee
Conference_Titel
Integration Technology, 2007. ICIT '07. IEEE International Conference on
Conference_Location
Shenzhen
Print_ISBN
1-4244-1092-4
Electronic_ISBN
1-4244-1092-4
Type
conf
DOI
10.1109/ICITECHNOLOGY.2007.4290470
Filename
4290470
Link To Document