A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation

A low Vmin, 6T-SRAM is realized in 28nm FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.52V for the 0.120um2 high density 6T-SRAM. Reduced read margin of the SRAM cell is recovered using a transient rise in cell supply level through word-line coupling. Write assist is realized using application of PVT selective negative bit-line approach. Bit-line is pulled to a required negative value in order to provide sufficient assistance for the write operation. Required power line overshoot is 50mV to ensure correct read operation. For write assist, the undershoot requirement is within 100mV. We could achieve a performance improvement of 50 percent with no power penalty for a 288Kb capacity SRAM with 2K words of 144bits width. The area overhead of the read and write assist scheme is 1.4 percent and 2.5 percent respectively.