On the optimum design of regulated cascode operational transconductance amplifiers

An optimal design procedure to achieve minimum power consumption for a given technology and gain bandwidth is presented. Regulated cascode gain enhancement is used to ensure sufficient DC-gain for minimum gate length transistors. To validate the approach five folded cascode OTA´s have been implemented, spanning a bias range of 1 /spl mu/A-10 mA, with measured unity-gain bandwidths within 20% of the designed value. For 17 mW at 3 V, a 0.5 /spl mu/m CMOS OTA achieves 630 MHz with 51/spl deg/ phase margin. The method has been applied in the design of a 3rd order /spl Delta//spl Sigma/ modulator for GSM receivers. The modulator consumes 2.8 mW at 3 V and has a dynamic range of 86 dB for a 100 kHz input signal bandwidth.