Trapping induced parasitic effects in GaN-HEMT for power switching applications

This paper summarizes our recent results on the analysis of the trapping-induced parasitic effects in GaN-based high electron mobility transistors for power switching applications. More specifically, we demonstrate the following relevant mechanisms: (i) dynamic R_on shows a significant increase when the devices are operated at high temperature levels; this effect is ascribed to a stronger trapping in the buffer region; (ii) the kinetics of buffer-related trapping processes can be effectively investigated by means of backgating tests, carried out at various temperature levels; (iii) buffer trapping is strongly correlated to drain-buffer vertical leakage. The reduction of vertical leakage is an important step towards the reduction of high temperature dynamic R_on. Finally, we demonstrate that by proper epitaxial design and device optimization it is possible to fabricate devices with very low dynamic R_on (measured at 150 °C, V_DS=500 V).