High-speed analog-to-digital converters in downscaled CMOS

High data-rate communications need high speed analog-to-digital converters. Recent flash and time interleaved SAR converters implemented in downscaled CMOS technologies have achieved GS/s conversion rates with very low power consumption. Flash ADCs can reach high speed with a single channel but the resolution is limited by exponential complexity and power consumption. SAR ADCs are well suited for higher resolution but, due to the sequential operation, require either massive interleaving or very fast technologies to achieve high speed. Hybrid architectures combine the advantages of different architectures to achieve the optimum compromise for a given resolution. In this paper the trade-offs between power, area and complexity for high speed designs are discussed and the potential of hybrid architectures is investigated.