40-Gbit/s D-type flip-flop and multiplexer circuits using InP HEMT

Author

Suzuki, T. ; Kano, H. ; Nakasha, Y. ; Takahashi, T. ; Imanishi, K. ; Ohnishi, H. ; Watanabe, Y.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

2001

fDate

20-22 May 2001

Firstpage

291

Lastpage

294

Abstract

We developed a novel design technique for a D-type flip-flop (D- FF) circuit that is based on a small-signal-equivalent circuit approach. This technique provides the best condition to operate the D-FF at a high frequency. Using this technique, we fabricated a master-slave D-FF using a 0.15-/spl mu/m InP HEMT technology. We achieved 40-Gbit/s operation with clear-eye-waveform patterns and reduced jitter.

Keywords

HEMT integrated circuits; III-V semiconductors; digital communication; equivalent circuits; field effect digital integrated circuits; flip-flops; high-speed integrated circuits; indium compounds; integrated circuit design; logic design; optical communication equipment; 0.15 micron; 40 Gbit/s; D-type flip-flop circuit; InP; InP HEMT technology; SCFL; master-slave flip-flops; multiplexer circuit; small-signal design technique; small-signal-equivalent circuit; Circuits; Clocks; FETs; Flip-flops; HEMTs; Indium phosphide; Latches; Multiplexing; Time division multiple access; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2001. Digest of Papers. 2001 IEEE

Conference_Location

Phoenix, AZ, USA

ISSN

1529-2517

Print_ISBN

0-7803-6601-8

Type

conf

DOI

10.1109/RFIC.2001.935696

Filename

935696