Title :
Static ultra low voltage CMOS logic
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate can be reduced to less than 10% compared to a static complementary gate.
Keywords :
CMOS logic circuits; high-speed integrated circuits; logic design; low-power electronics; circuit technique; energy efficient CMOS circuits; high speed CMOS circuits; logic depth; logic style; static complementary gate; static current consumption; static ultra low voltage CMOS logic; CMOS logic circuits; CMOS technology; Energy consumption; Informatics; Inverters; Leakage current; Logic circuits; Low voltage; Nanoelectronics; Threshold voltage;
Conference_Titel :
NORCHIP, 2009
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-4310-9
Electronic_ISBN :
978-1-4244-4311-6
DOI :
10.1109/NORCHP.2009.5397792
