Design representation and manipulation for high-level synthesis of DSP algorithms

Presents the new internal representation chosen for the high-level synthesis environment system under development at the Cefriel center. The aim of the work performed in Cefriel is to build a high-level synthesis environment constituted by a set of tools making it possible to perform synthesis of different classes of array architectures dedicated mainly to DSP (digital signal processing) applications. The basic representation to evaluate the best class of target architecture is a behavioral graph representation of the algorithm described in an HDL (hardware description language). This hierarchical representation and the algorithms that make it possible to manipulate it in order to identify the type of synthesis to be performed are discussed. The goal of the algorithms considered here is to modify the data flow graph and control flow graph in a way that will make easier the decision on the most suitable type of architecture to implement, given a specific algorithm and performance constraints. Structural synthesis can then be performed by the different modules of the environment. Orpheus, the systolic arrays synthesis module, is shown as an example