Title :
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process
Author :
Duc-Hung Le ; Sugii, Nobuyuki ; Kamohara, Shiro ; Xuan-Thuan Nguyen ; Ishibashi, Koichiro ; Pham, Cong-Kha
Author_Institution :
Univ. of Electro-Commun., Tokyo, Japan
Abstract :
In this paper, a design of 16-bit fixed-point digital signal processor (DSP) is proposed. This DSP is based on the Harvard architecture, having two buses for ALU and a pipeline multiply accumulator (MAC). It composes of 16 general purpose 24-bit registers together with 41 four-cycle instruction sets. The DSP has a simple structure which is compact and flexible. The DSP is designed for low-power consumption, and implemented on ASIC using SOTB 65nm process which is a kind of SOI devices. The DSP chip consumes very low-power consumption 282μW at the operation voltage 0.55V and operation frequency 200MHz.
Keywords :
application specific integrated circuits; digital signal processing chips; flip-flops; integrated circuit design; low-power electronics; pipeline processing; silicon-on-insulator; 24-bit registers; ASIC; DSP; Harvard architecture; MAC; SOI devices; SOTB process; digital signal processor; frequency 200 MHz; pipeline multiply accumulator; power 282 muW; silicon on thin box; size 65 nm; voltage 0.55 V; CMOS process; Clocks; Digital signal processing; Digital signal processors; Leakage currents; Power demand; Registers; DSP; Fixed-point; Low-power; SOTB;
Conference_Titel :
IC Design & Technology (ICICDT), 2015 International Conference on
Conference_Location :
Leuven
DOI :
10.1109/ICICDT.2015.7165918
