Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques

The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.