Compliant die-package interconnects at high frequencies

We investigate the concern that compliant interconnects due to their generally long, thin shape will introduce extra insertion loss for high-frequency signals, due to the added inductance at the die-package interface. We show that, as expected, an increase of the inductance in an inductive and resistive transition always causes additional insertion loss. However, in a complete system on-die drivers and receivers are connected to the die-package interface. Considering a capacitive and inductive-resistive transition, we show that for a given total pad capacitance there exists an optimal inductance that leads to a minimization of the insertion loss at the die-package interface. We refer to this as the pad capacitance compensation effect. As a significant finding, it appears that compliant interconnects can add some but not too much inductance at the die-package interface, so that the high-speed performance is actually improved. As an electromagnetically sound proof of the pad capacitance compensation concept, we perform full-wave simulations of variations of a generic die-package interface. Helical spring structures with different pitches and standard bumps are compared. Based on an appropriate post-processing of the simulation results the pad capacitance compensation effect for compliant interconnects is confirmed. As a final step, equivalent lumped-element representations (with frequency-dependent parameters) are derived directly from the simulated S parameters and a comparison with a 3-D quasistatic computation is made. This shows that the improved insertion loss for compliant interconnects is indeed correlated with an increased inductance of the structures.