DocumentCode
3273625
Title
Decimal counter based on redundancy-restraining technique
Author
Li-li, Zhao ; Mo-yi, Jia ; Xiao-dong, Yan
Author_Institution
Inf. Coll., Hebei Polytech. Univ., Tangshan, China
fYear
2011
fDate
15-17 April 2011
Firstpage
5787
Lastpage
5790
Abstract
In order to reduce the power dissipation correlative with redundant states in sequential circuits and the redundant leap of the lock, low power design of decimal counter is proposed in this paper. PSPICE simulation shows the design has correct logic function and low power dissipation.
Keywords
SPICE; logic design; sequential circuits; PSPICE simulation; decimal counter; logic function; low-power design; power dissipation reduction; redundancy-restraining technique; redundant lock leap; redundant states; sequential circuits; Clocks; Encoding; Flip-flops; Power demand; Radiation detectors; Sequential circuits; Synchronization; decimal counter; power; redundancy-restraining;
fLanguage
English
Publisher
ieee
Conference_Titel
Electric Information and Control Engineering (ICEICE), 2011 International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-8036-4
Type
conf
DOI
10.1109/ICEICE.2011.5777273
Filename
5777273
Link To Document