Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging

Post-silicon debugging efficiency is getting more critical to shorten the time-to-market than ever, as more bugs escape the verification in pre-silicon phase. Conventionally, simulation of corresponding low-level design description such as RTL or gate-level designs has been used to get observability and controllability. However, the simulation speed of such levels is very slow and the size of design description is very large compared to high-level design. In this paper, we first introduce an approach proposing to debug errors found in post-silicon phase using simulation of high-level designs, instead of low-level designs. To achieve the approach, we propose an I/O sequence mapping method that maps I/O sequences of chip executions to those of the corresponding high-level design. First, we give a formal definition of I/O sequence mapping and relevant notions. Then, based on the definition, we propose an I/O sequence mapping method by executing FSMs representing the interface specifications of the target design. We demonstrate that the proposed method can be effectively applied to several practical design examples with various interfaces.