Implementation aspects of fault-tolerant logic built with single-electron devices

Author

Flak, Jacek ; Laiho, Mika

Author_Institution

VTT Tech. Res. Centre of Finland, Espoo, Finland

fYear

2009

fDate

16-17 Nov. 2009

Firstpage

1

Lastpage

4

Abstract

This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by CMOS peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.

Keywords

CMOS integrated circuits; fault tolerant computing; integrated circuit interconnections; logic arrays; nanoelectronics; single electron devices; CMOS peripheries; binary programmable interconnections; fault-tolerant computing; fault-tolerant logic built; nanoscale logic array; single-electron devices; single-electron tunneling device; CMOS logic circuits; Computer architecture; Fault tolerance; Hardware; Logic arrays; Logic devices; Nanoscale devices; Programmable logic arrays; Single electron devices; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2009

Conference_Location

Trondheim

Print_ISBN

978-1-4244-4310-9

Electronic_ISBN

978-1-4244-4311-6

Type

conf

DOI

10.1109/NORCHP.2009.5397816

Filename

5397816