Innovative solutions to enable smaller substrate bump pad size for flip chip technology

Semiconductor technology is marching towards miniature size, but in contrast requires higher I/Os, which leads to growth in package size and die size for performance enhancement. Therefore the package designer needs to break the conventional design rule and innovate a way to fit more I/Os into the same package/die size, One of the key design rules that fits such criteria is substrate solder resist opening (SRO) design. It is the key element driving the die size and substrate size growth. By optimizing the solder resist opening dimension, the die size can reduce significantly to 15% less. However, when technology pushes the envelop to meet the criteria, a side effect surfaced, which relates to quality and reliability issues. The issues were found at silicon and package integration level. Various options and evaluations were carried out to enable the smaller SRO technology. The success of this project has brought the company significant cost savings for current and future products.