Low power design techniques for a Montgomery modular multiplier

This paper presents low power design techniques required to develop a high performance multiplier. Base on these techniques, a new architecture of a Montgomery modular multiplier is proposed. The architecture features two types of edge triggered D flip flops, a new clocking scheme and a pre-computation circuit designed to reduce the number of clock cycles required for each multiplication operation. Post layout simulation results indicate that the multiplier can operate at 1 GHz while delivering a high baud rate at minimal power consumption.