Title :
Message routing in 3D networks-on-chip
Author :
Rusu, Claudia ; Anghel, Lorena ; Avresky, Dimiter
Author_Institution :
TIMA Lab., CNRS-UJF-INP, Grenoble, France
Abstract :
Nowadays 3D chips are fabricated by stacking 2D layers and manufacturing vertical links between them. In this paper we present a routing scheme suited for 3D networks-on-chip (NoCs). It is based on the reuse of existing routing schemes for 2D NoCs. Our 3D scheme is scalable and can be used with any 2D topology. The effectiveness of the scheme for intra-layer communication is given by the respective 2D routing scheme of each layer, while for the inter-layer communication the scheme can always find a route between any source and destination, if there is one available.
Keywords :
message passing; network-on-chip; telecommunication network routing; 2D NoC; 2D layers stack; 2D routing scheme; 3D network-on-chip fabrication; interlayer communication scheme; intralayer communication scheme; message routing scheme; CMOS technology; Delay; Fault tolerance; Laboratories; Manufacturing; Network-on-a-chip; Routing; Safety; Stacking; Topology; 3D integration; network-on-chip; routing;
Conference_Titel :
NORCHIP, 2009
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-4310-9
Electronic_ISBN :
978-1-4244-4311-6
DOI :
10.1109/NORCHP.2009.5397855
