Near-optimum switched capacitor sample-and-hold circuit

Author

Centurelli, Francesco ; Simonetti, Andrea ; Trifiletti, Alessandro

Author_Institution

Dept. of Electron. Eng., Univ. of Rome La Sapienza, Rome, Italy

fYear

2009

fDate

16-17 Nov. 2009

Firstpage

1

Lastpage

4

Abstract

Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13 Â¿m CMOS technology featuring a signal to noise and distortion ratio (SNDR) of -75 dB at 12 Ms/s for a 1 Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity.

Keywords

CMOS analogue integrated circuits; integrated circuit layout; sample and hold circuits; switched capacitor networks; CMOS technology; analog cores; complementary metal-oxide-semiconductor; low-voltage flip-around sample-and-hold circuit; sample-and-hold simulation; signal to noise and distortion ratio; size 0.13 mum; switched capacitor architecture; switched capacitor sample-and-hold circuit; Analog-digital conversion; CMOS technology; Circuit noise; Circuit simulation; Circuit topology; Distortion; Pipelines; Signal to noise ratio; Switched capacitor circuits; Switching circuits; Active feedback; Analog-to-digital converters; Low-voltage; Sample-and-hold circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2009

Conference_Location

Trondheim

Print_ISBN

978-1-4244-4310-9

Electronic_ISBN

978-1-4244-4311-6

Type

conf

DOI

10.1109/NORCHP.2009.5397857

Filename

5397857