DocumentCode
3275476
Title
Incremental gate sizing for late process changes
Author
Lee, John ; Gupta, Puneet
Author_Institution
Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
fYear
2010
fDate
3-6 Oct. 2010
Firstpage
215
Lastpage
221
Abstract
Circuit design often runs in parallel with the development of the manufacturing process that will be used to fabricate it. However, as the manufacturing process matures, its models may undergo substantial changes as the design nears production. These changes may cause the design itself to fail its specifications, and in these cases it is necessary to perform an Engineering Change Order (ECO) to correct these problems. We present a new framework to perform incremental gate sizing for process changes late in the design cycle. This includes a method to measure and estimate ECO cost, transform these costs into a linear programming optimization problem, and solve the problem to find the ECO. This method performs well, compared to a leading commercial physical design tool, reducing ECO costs by 18% to 99% in changed area, and 1% to 96% in number of pins with unnecessary pin timing changes.
Keywords
design engineering; linear programming; manufacturing processes; circuit design; design cycle; engineering change order; incremental gate sizing; late process change; linear programming optimization; manufacturing process; Algorithm design and analysis; Benchmark testing; Delay; Layout; Logic gates; Pins;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2010 IEEE International Conference on
Conference_Location
Amsterdam
ISSN
1063-6404
Print_ISBN
978-1-4244-8936-7
Type
conf
DOI
10.1109/ICCD.2010.5647778
Filename
5647778
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