Title :
Design of low phase noise and fast locking PLL frequency synthesizer
Author :
Xu, Xiaoliang ; Liu, Huihua ; Ao, Siyan
Author_Institution :
Res. Inst. of Electron. Sci. & Technol., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
Third-order charge-pump PLL frequency synthesizer is designed, considering phase noise and lock time. Using of bandwidth optimization, dead-zone eliminated, high-match charge pump, and low noise oscillator design methods to optimize system phase noise and also reduce lock time. Test shows that PLL frequency synthesizer output phase noise is - 96.2 dBc@1MHz, RMS jitter is 1.4ps, and lock time is about 2us.
Keywords :
bandwidth allocation; charge pump circuits; frequency synthesizers; optimisation; oscillators; phase locked loops; phase noise; bandwidth optimization; dead-zone eliminated design methods; fast locking PLL frequency synthesizer; high-match charge pump design methods; lock time; low noise oscillator design methods; low phase noise design; output phase noise; third-order charge-pump PLL frequency synthesizer; Charge pumps; Frequency synthesizers; Phase locked loops; Phase noise; Solid state circuits; Voltage-controlled oscillators; Charge Pump VCO; Frequency Synthesizer; PLL; Phase noise;
Conference_Titel :
Electric Information and Control Engineering (ICEICE), 2011 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-8036-4
DOI :
10.1109/ICEICE.2011.5777391
