Self-testing and self-reconfiguration architecture for 2-D WSI arrays

A self-testing and self-reconfiguration method for both production and field repair for a 2-D wafer scale integration (WSI) array is presented. A distributed built-in-self-test (BIST) tests all processing elements (PEs) of the wafer simultaneously. While some techniques use local BIST at each individual PE, such BIST cannot test the interconnection network. A global bypass-through bus is used to communicate data simultaneously to all PEs. Multiple input shift registers (MISRs) for random test generation are used where only 2m MISRs are needed for m×m array of PEs. In this design, the overhead consists of two simple multiplexers, two registers, a simple maintenance control logic and a comparator for each PE. A guided ripple replacement (GRR) reconfiguration technique is used with a maximum interconnection edge of 2D length, where D is the diagonal distance in the largest area of clustered defected PEs. This upper limit length is optimal. The algorithm is capable of dealing with heavily clustered defects. The approach optimizes the area overhead and performance, by sharing the control network to perform reconfiguration after testing the PEs. The array structure can be flexibly designed to accommodate different reconfiguration techniques without significant modification