Testable design of bit-level systolic block FIR filters

Author

Wu, Cheng-Wen ; Wang, Jen-Chuan

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

3

fYear

1992

fDate

10-13 May 1992

Firstpage

1129

Abstract

A design-for-testability approach for VLSI cellular arrays, based on M-testability conditions, is applied to bit-level systolic block FIR (finite impulse response) filters. M-testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. The authors illustrate this approach on bit-level systolic arrays which implement block FIR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size

Keywords

CMOS integrated circuits; design for testability; digital filters; integrated circuit testing; systolic arrays; two-dimensional digital filters; 2D filters; CMOS circuits; M-testability conditions; VLSI cellular arrays; bit-level systolic block FIR filters; design-for-testability; linear filters; single-cell-fault testability; Automatic testing; Built-in self-test; Digital filters; Digital signal processing; Finite impulse response filter; Hardware; Logic arrays; Nonlinear filters; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230328

Filename

230328