Design in the nano-scale Era: Low-power, reliability, and error resiliency

Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single chip. However, scaling is facing several problems - severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. We believe that device aware circuit and architecture design along with statistical design techniques can provide large improvement in power dissipation (Vdd scaling) while providing the required reliability and yield. In this talk I will present design techniques to address power and reliability problems in scaled technologies for both logic and memories.