Two-phase decimation and jitter compensation in full-duplex data transceivers [for ISDN]

Describes the technique of two-phase decimation. When combined with the previously known technique of jitter compensation, it allows the performance of the echo canceler in a full-duplex data transceiver to be preserved in the presence of both the phase steps generated by the timing recovery digital phase locked loop and rapid changes in the sampling phase of the input signal. This results from being able to train the jitter canceler continuously, instead of restricting the training to some initial startup period. This technique provides an efficient way to preserve the time invariance of the echo path during a phase step, a precondition for the jitter compensation technique to perform properly