Accurate power estimation of hardware co-processors using system level simulation

Managing power consumption in a System-On-Chip (SoC) design is becoming increasingly important. SoCs generally consist of various co-processors. Accurate power estimation of these co-processors at the highest possible abstraction level helps in performing early power-aware design tradeoffs. This paper presents a methodology to create abstract statistical power models for hardware co-processors and its utilization at system-level for power estimation. In our system-level design environment co-processors are realized as Finite State Machine with Datapath (FSMD) and co-simulated with simulation model of ARM processor. Our power modeling methodology comprises of a learning and utilization phase. In the learning phase, we obtain state specific combinational signal toggling statistics from the FSMD simulation and derive a regression based power model. Consequently, we utilize this power model of FSMD in the full-chip simulation for faster computation of power estimates based on the activities of the FSMD model. Through a number of experimental designs, we show that with a relatively short learning phase no more than 6% worst-case and 4% rms error is observed with respect to the RTL power estimation techniques.