Sequential circuits with combinational test generation complexity

We propose a new design for testability (DFT) technique which, like full scan design, guarantees that tests can be derived using a combinational test generator. Our DFT technique has two important advantages over full scan design: (1) the area overhead incurred by our technique is significantly less and (2) the test application time for our technique is significantly lower. This DFT technique selects scan flip-flops and/or test points such that, in the test mode, the circuit will belong to a special class of sequential circuits that we call strongly balanced structures. We give a simple characterization for strongly balanced structures and provide efficient methods to select scan flip-flops and/or test points to reduce any sequential circuit to a strongly balanced structure. A complete test set can be obtained for a strongly balanced structure using a combinational test generator. Experimental results on ISCAS 89 benchmark circuits and production VLSI circuits show that both the DFT overhead and the test application time are substantially lower for our technique