Variation aware low power buffered interconnect design

Enhancing interconnect robustness against variations is crucial to system performance and reliability in sub-65 nm technologies. We present a new interconnect design methodology to optimize power consumption and robustness during buffer insertion. Using closed form expressions for interconnect delay and delay variation, we construct a design space for the interconnect. Through power-robustness tradeoff analysis of the design space, the buffering solution that minimizes power consumption while satisfying the delay and robustness constraints is computed. Comparisons with SPICE simulations show the effectiveness of this technique.